Struct pci_types::PciPciBridgeHeader

pub struct PciPciBridgeHeader(/* private fields */);

PCI-PCI Bridges have a Type-1 header, so the remainder of the header is of the form:

    32                           16                              0
    +-----------------------------------------------------------+ 0x00
    |                                                           |
    |                Predefined region of header                |
    |                                                           |
    |                                                           |
    +-----------------------------------------------------------+
    |                  Base Address Register 0                  | 0x10
    |                                                           |
    +-----------------------------------------------------------+
    |                  Base Address Register 1                  | 0x14
    |                                                           |
    +--------------+--------------+--------------+--------------+
    | Secondary    | Subordinate  |  Secondary   | Primary Bus  | 0x18
    |Latency Timer | Bus Number   |  Bus Number  |   Number     |
    +--------------+--------------+--------------+--------------+
    |      Secondary Status       |  I/O Limit   |   I/O Base   | 0x1C
    |                             |              |              |
    +-----------------------------+--------------+--------------+
    |        Memory Limit         |         Memory Base         | 0x20
    |                             |                             |
    +-----------------------------+-----------------------------+
    |  Prefetchable Memory Limit  |  Prefetchable Memory Base   | 0x24
    |                             |                             |
    +-----------------------------+-----------------------------+
    |             Prefetchable Base Upper 32 Bits               | 0x28
    |                                                           |
    +-----------------------------------------------------------+
    |             Prefetchable Limit Upper 32 Bits              | 0x2C
    |                                                           |
    +-----------------------------+-----------------------------+
    |   I/O Limit Upper 16 Bits   |   I/O Base Upper 16 Bits    | 0x30
    |                             |                             |
    +-----------------------------+--------------+--------------+
    |              Reserved                      |  Capability  | 0x34
    |                                            |   Pointer    |
    +--------------------------------------------+--------------+
    |                  Expansion ROM base address               | 0x38
    |                                                           |
    +-----------------------------+--------------+--------------+
    |    Bridge Control           |  Interrupt   | Interrupt    | 0x3C
    |                             |     PIN      |   Line       |
    +-----------------------------+--------------+--------------+

Implementations

impl PciPciBridgeHeader

pub fn from_header( header: PciHeader, access: &impl ConfigRegionAccess ) -> Option<PciPciBridgeHeader>

pub fn header(&self) -> PciHeader

pub fn status(&self, access: &impl ConfigRegionAccess) -> StatusRegister

pub fn command(&self, access: &impl ConfigRegionAccess) -> CommandRegister

pub fn update_command<F>(&self, access: &impl ConfigRegionAccess, f: F)

where F: Fn(CommandRegister) -> CommandRegister,

pub fn primary_bus_number(&self, access: &impl ConfigRegionAccess) -> u8

pub fn secondary_bus_number(&self, access: &impl ConfigRegionAccess) -> u8

pub fn subordinate_bus_number(&self, access: &impl ConfigRegionAccess) -> u8